A Non Pipelined System Takes 100 Ns to Process a Task. The Same Task
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A nonpipelined system takes 200ns to process a task. The same task can be processed in a 5-segment p 1 answer below »
A nonpipelined system takes 200ns to process a task. The same task can be processed in a 5-segment pipeline with a clock cycle of 40ns. Determine the speedup ratio of the pipeline for 200 tasks. What is the maximum speedup that could be achieved with the pipeline unit over the nonpipelined unit? A nonpipeline system takes 100ns to process a task. The same task can be processed in a 5-stage pipeline with a clock cycle of 20ns. Determine the speedup ratio of the pipeline for 100 tasks. What is the theoretical speedup that could be achieved with the pipeline system over a nonpipelined system? Write code to implement the expression A = (B + C) times (D + E) on 3-, 2-, 1-, and 0- address machines. In accordance with programming language practice, computing the expression should not change the values of its operands. A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. How many bits are needed for the opcode? How many bits are left for the address part of the instruction? What is the maximum allowable size for memory? What is the largest unsigned binary number that can be accommodated in one word of memory? The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with 4 fields: an opcode field; a mode field to specify 1 of 7 addressing modes; a register address field to specify 1 of 60 registers; and a memory address field. Assume an instruction is 32 bits long. Answer the following: How large must the mode field be? How large must the register field be? How large must the address field be? How large is the opcode field? Suppose an instruction takes four cycles to execute in a nonpipelined CPU: one cycle to fetch the instruction, one cycle to decode the instruction, one cycle to perform the ALU operation, and one cycle to store the result. In a CPU with a 4-stage pipeline, that instruction still takes four cycles to execute, so how can we say the pipeline speeds up the execution of the program? Pick an architecture (other than those covered in this chapter). Do research to find out how your architecture approaches the concepts introduced in this chapter as was done for Intel, MIPS, and Java. Most computers typically fall into one of three types of CPU organization. (1) general register organization; (2) single accumulator organization; or (3) stack organization. The advantage of zero-address instruction computers is that they have short programs; the disadvantage is that the instructions require many bits, making them very long.
A Non Pipelined System Takes 100 Ns to Process a Task. The Same Task
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